Semiconductor Structures

ABSTRACT

The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.

TECHNICAL FIELD

The invention pertains to semiconductor structures, and to methods offorming semiconductor constructions.

BACKGROUND OF THE INVENTION

Semiconductor memory constructions typically comprise arrays oftightly-spaced lines (bitlines and wordlines), together with datastorage structures. For instance, dynamic random access memory (DRAM)comprises tightly-spaced wordlines and bitlines together withcapacitors, with the capacitors being utilized as data storage devices.

The semiconductor memory constructions are typically integrated withother circuitry on a single semiconductor chip. Such other circuitry isprovided peripherally to the memory array, and can be utilized, forexample, for reading of information from the memory array or writing ofinformation to the memory array.

Continuing goals during semiconductor chip fabrication are to increasethe level of integration while maintaining, or even improving, deviceperformance; to increase device throughput; and to reduce costs.Accordingly, it is desirable to develop improved methods for fabricationof integrated circuitry. It is also desirable to develop integratedcircuitry having improved performance characteristics.

SUMMARY OF THE INVENTION

In one aspect, the invention encompasses a method of forming asemiconductor construction. A substrate is provided to have a definedmemory array region. The substrate comprises, within the memory arrayregion, a plurality of storage node contacts within an insulativematerial. The storage node contacts have uppermost surfaces covered bythe insulative material. Trenches are formed within the insulativematerial. Electrically conductive bitline material is formed to fill thetrenches. The bitline material is patterned into a plurality of spacedbitlines. At least portions of individual bitlines are elevationallyabove the storage node contact uppermost surfaces. Insulative caps areformed within the trenches and over the bitlines. After the bitlinematerial is formed, and before the insulative caps are formed,electrically conductive structures are formed to extend through theinsulative material in locations between the bitlines. The electricallyconductive structures extend to the storage node contacts.

In one aspect, the invention encompasses yet another method of forming asemiconductor construction. A substrate is provided to have a definedmemory array region. The substrate comprises, within the memory arrayregion, a plurality of storage node contacts covered by an insulativematerial. Trenches are formed within the insulative material. Thetrenches have faceted upper portions. The facets slope upwardly andoutwardly relative to the trenches. Uppermost and outermost facetededges of adjacent trenches are spaced from one another by interveningregions of the insulative material. The trenches are filled withelectrically conductive bitline material. The bitline material extendsover the trench faceted portions but not over the intervening regions ofthe insulative material. The bitline material is utilized as an etchmask during an etch to form first openings extending through theintervening insulative material to the storage node contacts. A fillermaterial is formed within the first openings. After the filler materialis formed, the bitline material is recessed within the trenches to formunfilled regions of the trenches above the bitline material. Insulativecaps are formed within the unfilled regions of the trenches over thebitline material. After the insulative caps are formed, at least some ofthe filler material is removed to form second openings extending to thestorage node contacts. Electrically conductive material is formed withinthe second openings and electrically coupled to the storage nodecontacts.

In one aspect, the invention includes a semiconductor structure. Thestructure comprises a substrate which includes a plurality of storagenode contacts within an insulative material. A plurality of trenches arewithin the insulative material, with the trenches having faceted topportions. The electrically conductive bitlines extend within thetrenches. The bitlines only partially fill the trenches. At leastportions of individual bitlines are elevationally above the storage nodecontacts. The bitlines are a plurality of bitlines, with adjacentbitlines being spaced from one another by intervening locations.Insulative caps are within the trenches and over the bitlines.Electrically conductive columns extend through the insulative materialin the intervening locations between the bitlines. The electricallyconductive columns are electrically coupled with the storage nodecontacts. The faceted top portions of the trenches slope outwardly andupwardly from the trenches, and uppermost surfaces of the facetedportions are directly against the electrically conductive columns.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic, cross-sectional view of a semiconductor waferfragment at a preliminary processing stage of an exemplary aspect of anembodiment of the present invention.

FIG. 2 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 1.

FIG. 3 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 2.

FIG. 4 is an expanded region of the FIG. 3 wafer fragment, with suchexpanded region being diagrammatically illustrated in FIG. 3 as theregion “4”.

FIG. 5 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 3.

FIG. 6 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 5.

FIG. 7 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 6.

FIG. 8 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 7.

FIG. 9 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 8.

FIG. 10 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 9.

FIG. 11 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 10.

FIG. 12 is a view of the FIG. 1 wafer fragment shown at a processingstage subsequent to that of FIG. 11.

FIG. 13 is a diagrammatic, cross-sectional view of the FIG. 1 waferfragment shown at a processing stage identical to that of FIG. 6, and isa starting point for discussion of a second embodiment aspect of thepresent invention.

FIG. 14 is a view of the FIG. 13 wafer fragment shown at a processingstage subsequent to that of FIG. 13.

FIG. 15 is a view of the FIG. 13 wafer fragment shown at a processingstage subsequent to that of FIG. 14.

FIG. 16 is a view of the FIG. 13 wafer fragment shown at a processingstage subsequent to that of FIG. 15.

FIG. 17 is a view of the FIG. 13 wafer fragment shown at a processingstage subsequent to that of FIG. 16.

FIG. 18 is a view of the FIG. 13 wafer fragment shown at a processingstage subsequent to that of FIG. 17.

FIG. 19 is a view of the FIG. 13 wafer fragment shown at a processingstage subsequent to that of FIG. 18.

FIG. 20 is a diagrammatic view of a computer illustrating an exemplaryapplication of the present invention.

FIG. 21 is a block diagram showing particular features of themotherboard of the FIG. 20 computer.

FIG. 22 is a high-level block diagram of an electronic system accordingto an exemplary aspect of the present invention.

FIG. 23 is a simplified block diagram of an exemplary memory deviceaccording to an aspect of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

In some aspects the invention can be considered to comprise methods inwhich a disposable hard mask is utilized in conjunction with a damasceneprocess so that a self-aligned contact etch can be used during localinterconnect fabrication. A standard damascene flow can be utilized inconjunction with incorporation of an additional etch to create a flared(i.e., faceted, prograde) top etch profile. Such creates an overhangadjacent damascene-formed trenches. When the trenches are filled withmaterial, the material creates self-aligning spacers on the overhang.The self-aligning spacers can then be used for self-aligned contactetches. At some point in the process, conductive material can beprovided within the trenches and etched back to form bitlines.Insulative material can then be provided over the conductive material toprovide an insulative surface that can subsequently be utilized tosupport capacitor constructions, such as, for example,container-capacitor constructions. In some aspects, the containers canbe formed with a high-margin process since the bitlines are buriedbeneath the insulative material prior to fabrication of the capacitors.Particular aspects of the invention can advantageously formself-aligning spacers, and enable the spacers to be formedsimultaneously with other process steps.

Particular exemplary aspects of the invention are described withreference to FIGS. 1-23.

Referring initially to FIG. 1, a semiconductor wafer fragment 10 isillustrated at a preliminary processing stage. Wafer fragment 10comprises a substrate 12. Such substrate can, for example, comprisemonocrystalline silicon lightly-doped with background p-type dopant. Toaid in interpretation of the claims that follow, the terms“semiconductive substrate” and “semiconductor substrate” are defined tomean any construction comprising semiconductive material, including, butnot limited to, bulk semiconductive materials such as a semiconductivewafer (either alone or in assemblies comprising other materialsthereon), and semiconductive material layers (either alone or inassemblies comprising other materials). The term “substrate” refers toany supporting structure, including, but not limited to, thesemiconductive substrates described above.

An insulative material 14 is provided over substrate 12, and a pluralityof electrically conductive interconnects 16 are within the insulativematerial. Interconnects 16 can correspond to storage node contacts, andspecifically can ultimately be utilized for electrically couplingcapacitor storage nodes with other circuitry. The storage node contacts16 are shown electrically connected to circuitry 18. Such circuitry cancorrespond to transistor devices associated with wordlines.Specifically, the transistor devices can have source/drain regions whichelectrically couple with the conductive columns 16, and which ultimatelyare utilized for passing bits of data to and from capacitors that arealso coupled with the columns 16.

Insulative material 14 can comprise any suitable composition orcombination of compositions, and in particular aspects will comprise,consist essentially of, or consist of borophosphosilicate glass.

Electrically conductive columns 16 can comprise any suitable compositionor combination of compositions, and in particular aspects will comprise,consist essentially of, or consist of conductively-doped silicon.

Storage node contacts 16 comprise uppermost surfaces 17. Such uppermostsurfaces are part of a planarized surface 19 that extends across storagenodes contacts 16 and insulative material 14.

A second insulative material 20 extends over planarized surface 19, andaccordingly extends over insulative material 14 and storage nodecontacts 16. Insulative material 20 can be an etch stop in subsequentprocessing, and can comprise, consist essentially of, or consist of, forexample, silicon nitride or silicon dioxide formed fromtetra-ethyl-ortho-silicate (TEOS). In some aspects, insulative materials14 and 20 can be together considered to be a single insulative materialcomprising the composition of layer 20 over the composition of layer 14.In such aspects, storage node contacts 16 can be considered to be withinthe insulative material comprising combined layers 14 and 20, and tohave the uppermost surfaces covered by such insulative material.

A third insulative material 22 is over insulative material 20.Insulative material 22 can comprise any suitable composition orcombination of compositions, and in particular aspects will comprise,consist essentially of, or consist of borophosphosilicate glass (BPSG)and/or phosphosilicate glass (PSG). Preferably, insulative materials 22and 20 are of suitable composition relative to one another such thatmaterial 22 can be selectively etched relative to material 20.

The construction 10 is shown divided into two defined regions 4 and 6,with a dashed line 7 diagrammatically separating such two definedregions from one another. The defined region 6 can correspond to amemory array region of the construction, and the region 4 can correspondto a region understood to be peripheral to the memory array region. Inparticular aspects of the invention, DRAM circuitry is formed within thememory array region 6, and peripheral circuitry is formed within theperipheral region 4.

Referring next to FIG. 2, a trench 24 is formed within the peripheralregion 4 to extend through insulative materials 14 and 20, and a widertrench 26 is formed over trench 24 to extend through insulative material22 and to stop on material 20. Additionally, trenches 28 are formed toextend through insulative material 22 in memory array region 6, and tostop on layer 20. Trenches 24, 26 and 28 can be formed utilizingstandard damascene processing.

Referring next to FIG. 3, material 22 is subjected to an etch whichforms faceted upper portions 30 of trench 26, and faceted upper portions32 of trenches 28. If material 22 comprises, consists essentially of, orconsists of a silicon oxide (such as, for example, BPSG) the facet etchcan be accomplished utilizing the following conditions:

-   -   argon or fluorine gas at a flow rate of from about 2 standard        cubic centimeters per minute (sccm) to about 500 sccm;    -   CF₄O at a flow rate of from 0 to about 500 sccm;    -   CH₂F₂ at a flow rate of from 0 to about 500 sccm    -   pressure of from about 1 milliTorr to about 5000 milliTorr; and    -   power of from about 5 watts to about 5000 watts.

It is to be understood, however, that any suitable chemistry can beutilized for the facet etch. For instance, O₂ can be utilized to facetetch a resist, and then standard oxide etch chemistry can be utilized totransfer the facets to underlying oxide. Also, in some aspects an argonpresputter can also be utilized to accomplish the facet etch.

FIG. 4 shows an expanded region of FIG. 3, and is utilized to illustratevarious aspects of facets of exemplary embodiments of the presentinvention. In the cross-sectional view of FIG. 4, it can be seen thatthe shown trench 28 has a bottom periphery with a horizontally-extendingwidth “W”. Such width can be, for example, at least about 50 Å; in somecases from about 50 Å to about 500 Å; from about 50 Å to about 1000 Å;or from about 50 Å to about 500 Å. Also in the shown cross-sectionalview, the trench has a pair of facets 32 on opposing sides of the trenchrelative to one another. The facet on the shown left side of the trenchhas a horizontally-extending width “X”, and the facet on the right sideof the trench has a horizontally extending width “Y”. Dimensions of thehorizontally extending widths X and Y can be from about 10% to about400% of the dimension of horizontally extending width “W”, and can be,for example, from about 10% to about 50% of the horizontally-extendingwidth “W”, or in particular aspects can be from about 15% to about 25%of the horizontally-extending width “W”. In some aspects, each of thewidths “X” and “Y” can be from about 50 Å to about 300 Å, and inparticular aspects can be from about 100 Å to about 300 Å.

The shown facets can be considered to extend upwardly and outwardlyrelative to the trench 28 with which the facets are associated. In otherwords, each of the shown facets can be considered to have a slope whichextends upwardly and outwardly relative to a vertical sidewall of thetrench with which the facets are associated. The vertical sidewalls arelabeled as 34 in the FIG. 4 view. A vertically-extending sidewall can beconsidered to define a normal axis. Exemplary normal axes are shownextending upwardly beyond the sidewalls, with the extensions of thenormal axes being shown in dashed lines and labeled as 35 in the FIG. 4view. For purposes of interpreting this disclosure and the claims thatfollow, a faceted portion of a trench is defined as a portion of thetrench having a slope angled at from about 10° to about 80° relative toa normal axis defined by a sidewall (specifically, a substantiallyvertical sidewall) of the trench (with the angles between the facetslopes and the normal axes defined by the sidewalls being designated bythe label 37 in FIG. 4), with the facet of the faceted portion being thesurface sloped at from about 10° to about 80° relative to the normalaxis defined by the sidewall. A typical of a facet angle slope to thenormal axis defined by a sidewall will be from about 10° to about 45°.In particular aspects the angle of a facet surface slope to a normalaxis defined by a sidewall 34 will be greater than 20° and less than orequal to about 45°; and in some aspects the angle of a facet surfaceslope to a normal axis defined by a sidewall 34 will be greater than 30°and less than or equal to about 45°.

Referring back to FIG. 3, the insulative material 22 between adjacenttrenches of the memory array region 6 forms pillars 40 having uppermostedges 41. The faceted portions have uppermost and outermost edges (orcorners) 43, and the uppermost and outermost faceted portion edges 43 ofadjacent trenches are spaced from one another by intervening regions ofinsulative material corresponding to the uppermost surfaces 41 ofpillars 40.

Referring to FIG. 5, electrically conductive material is formed withintrenches 26 and 28, over the facets 30 and 32, and over the interveningregions 41 between adjacent faceted portions. The shown conductivematerial comprises three compositions 46, 48 and 50. Composition 46 cancomprise, consist essentially of, or consist of titanium; composition 48can comprise, consist essentially of, or consist of titanium nitrideand/or tungsten nitride; and composition 50 can comprise, consistessentially of, or consist of tungsten. The conductive material of thecombined compositions 46, 48 and 50 can be referred to as a material46/48/50. Such material can be considered a bitline material, in thatthe material is ultimately patterned into bitlines. Although the bitlinematerial is shown comprising three compositions, it is to be understoodthat any suitable conductive material can be utilized. For instance,metal silicide (such as, for example, tungsten silicide) can beincorporated into the bitline material in addition to, or alternativelyto, one of the stated compositions 46, 48 and 50.

Referring next to FIG. 6, construction 10 is subjected to planarization(such as, for example, chemical-mechanical polishing) to form aplanarized upper surface 51 extending across insulative material 22 andacross the conductive material 46/48/50. The planarization removes theconductive material from over the intervening regions 41 between thefaceted portions while leaving the conductive material within thetrenches 26 and 28, and over the faceted portions 30 and 32.

It is noted that the intervening regions 41 are directly over conductivepedestals 16. Accordingly the planarization of the conductive material46/48/50 has removed the material from directly over storage nodecontacts 16, while leaving trenches 26 and 28 substantially filled withthe conductive material.

The bitline material 46/48/50 at the processing stage of FIG. 6 can beconsidered to be provided to fill trenches 28, extend over faceted topportions of the trenches, and not extend over the locations 41. In someaspects, locations 41 can be considered node interconnect locations, inthat electrically conductive interconnects are ultimately formed toextend through locations 41 and to contact conductive nodescorresponding to conductive columns 16.

It is noted that in the shown aspect of the invention trench 26 has beenformed substantially simultaneously with trenches 28 (FIG. 2), and hasbeen filled with conductive material 46/48/50 substantiallysimultaneously with the filling of trenches 28.

Referring next to FIG. 7, a mask 54 is provided to protect peripheralregion 4 of construction 10. Subsequently, conductive material 46/48/50is utilized as another mask during an etch to form openings 56 extendingthrough the intervening regions 41 (FIG. 6) of insulative material 22,through insulative material 20, and to the uppermost surfaces 17 ofstorage node contacts 16. The conductive material 46/48/50 extendingacross faceted regions 32 forms overhangs which act as a hard mask, andaccordingly openings 56 can be considered to be self-aligned relative tothe bitline material 46/48/50 within trenches 28. It is noted that theself-alignment is in the plane of the shown cross-sectional view of FIG.7, and that there typically would not be self-alignment orthogonally tosuch plane, (i.e., in and out of the page of the shown view of FIG. 7).Accordingly, additional masking (not shown) would be utilized toaccomplish desired alignments orthogonally to the plane of the view ofFIG. 7.

Referring next to FIG. 8, mask 54 (FIG. 7) is removed. Subsequently, aconductive material 60 is formed to extend over bitline material46/48/50 and insulative material 22, and to extend within openings 56 tophysically contact the uppermost surfaces of storage node contacts 16.Material 60 can comprise any suitable conductive composition orcombination of compositions, and in particular aspects will compriseconductively-doped silicon. The silicon can be conductively-doped asdeposited, or can be deposited in a substantially undoped form andsubsequently doped by any suitable methodologies, (such as, for example,implanting).

Referring next to FIG. 9, material 60 is subjected to planarization(such as, for example, chemical-mechanical polishing) to remove material60 from over bitline material 46/48/50 and insulative material 22. Suchleaves material 60 within intervening regions between trenches 28 aselectrically conductive interconnects. The interconnects extend fromdirect physical contact with storage node contacts 16 to a planarizeduppermost surface 61 extending across construction 10. The interconnectscan be considered to be electrically conductive columns or structuresbetween trenches 28.

Referring next to FIG. 10, bitline material 46/48/50 is recessed withintrenches 26 and 28. Such can be accomplished with an etch selective formaterials 46/48/50 relative to materials 22 and 60, and/or by providinga patterned mask (not shown) to protect materials 22 and 60 during theetch of bitline material 46/48/50. In exemplary aspects, the etch ofbitline material 46/48/50 will utilize an ammonium peroxide mixture(which is generally selective for metals relative to oxides of silicon)and/or a dry etch.

The reduction in height of bitline material 46/48/50 forms openings inthe trenches 26 and 28 above the remaining bitline material, andpatterns bitlines within trenches 28 from the remaining material46/48/50. Trenches 28 can be initially formed to a total depth “D” offrom about 1000 Å to about 6000 Å, and the remaining depth “R” afterreduction of the height of bitline material 46/48/50 can be from about5000 Å to about 3000 Å. The remaining depth “R” is typically from about750 Å to about 1250 Å, with a common dimension being about 1000 Å.

Referring next to FIG. 11, insulative caps 64 are formed within openings26 and 28, and over the recessed bitline material 46/48/50. Such capscan be formed by providing an insulative material over material 22 andwithin openings 26 and 28, and subsequently subjecting the material toplanarization to form the shown planarized upper surface 65 extendingacross material 22 and material 64. Insulative material 64 can compriseany suitable composition or combination of compositions, and inparticular aspects will comprise, consist essentially of, or consist ofsilicon nitride.

Referring next to FIG. 12, an insulative material 70 is formed overplanarized surface 65, and subsequently capacitor structures 72, 74, 76and 78 are formed within the insulative material. Each of the capacitorstructures comprises a first electrode (82, 84, 86 and 88), a dielectricmaterial (92, 94, 96 and 98) and a second electrode (99). The firstelectrodes 82, 84, 86 and 88 will be recognized by persons of ordinaryskill in the art as being storage nodes. Accordingly, the conductivecolumns of material 60 connect storage nodes of capacitors 72, 74, 76and 78 with the storage node contacts 16, and ultimately with thecircuitry 18. As discussed previously, circuitry 18 can comprisetransistor devices, and accordingly the construction of FIG. 12 cancomprise capacitor constructions electrically coupled with transistordevices through the interconnecting storage node contacts 16 andconductive material 60. As will be recognized by persons of ordinaryskill in the art, a capacitor coupled to a transistor device is a unitcell of a DRAM. Accordingly, the construction of FIG. 12 can comprise aplurality of DRAM unit cells associated with memory region 6. Each ofthe capacitors 72, 74, 76 and 78 is in one-to-one correspondence with aconductive column of material 60. The capacitors are shown ascontainer-type capacitors, but it is to be understood that any suitablecapacitor type can be utilized.

FIGS. 1-12 illustrate one aspect in which faceted portions associatedwith trenches are utilized during fabrication of bitlines and conductivepedestals between the bitlines. Another exemplary aspect is describedwith reference to FIGS. 13-19.

Referring initially to FIG. 13, construction 10 is illustrated at aprocessing stage identical to that of the above-discussed FIG. 6. Theconstruction 10 of FIG. 13 is, however, shown comprising a conductivematerial 100 in place of material 46/48/50 of FIG. 6. Such change inprovided for convenience, and it is to be understood that the material100 of FIG. 13 can, and typically would, comprise the material 46/48/50discussed above with reference to FIG. 6.

Referring next to FIG. 14, material 100 has been utilized as a maskduring an etch of materials 20 and 22. A suitable etch is an anisotropicoxide/nitride dry etch, with material 100 comprising tungsten andfunctioning as a hard mask. The etch forms self-aligned spacers from thematerial 22 remaining against material 100 and under the facetedportions 30 and 32. The alignment of the spacers formed from material 22relative to material 100 is within the plane of the cross-sectional viewof FIG. 14. It is noted that some self-alignment can also occur indirections orthogonal to the shown cross-sectional view (i.e.,directions in and out of the page relative to the shown cross-sectionalview).

The etch of materials 20 and 22 forms pedestals 102, 104, 106, 108 and110 comprising conductive material 100 and adjacent material 22 spacers.The etch also forms openings 112 and 114 adjacent the pedestal 102associated with peripheral region 4; and forms openings 116, 118 and 120between the pedestals 104, 106, 108 and 110 associated with the memoryarray region 6 of the substrate. The openings 116, 118 and 120 extenddown to upper surfaces 17 of storage node contacts 16.

Referring next to FIG. 15, an electrically insulative material 122 isprovided within the openings 112, 114, 116, 118 and 120. Insulativematerial 122 can comprise, consist essentially of, or consist of, forexample, a spin-on dielectric and/or silicon dioxide which has not beenspun-on.

Construction 10 is shown having a planarized upper surface 123 at theprocessing stage of FIG. 15. Such can be accomplished by forminginsulative material 122 to extend over material 100 and within theopenings 112, 114, 116, 118 and 120, and subsequently subjectingconstruction 10 to planarization (such as, for example,chemical-mechanical polishing) to form the planarized upper surface.

Referring next to FIG. 16, conductive material 100 is subjected to anetch which reduces the height of the conductive material within trenches26 and 28, and which accordingly reopens portions of trenches 26 and 28above the remaining portion of conductive material 100. The etch ofconductive material 100 can be identical to an etch of material 46/48/50discussed above with reference to FIG. 10. In particular aspects,material 100 will predominately comprise tungsten, and the etch cancomprise a tungsten etch-back of the conductive material.

Referring next to FIG. 17, an insulative material 130 is provided tofill the portions of trenches 26 and 28 over recessed material 100.Insulative material 130 can comprise, consist essentially of, or consistof, for example, silicon nitride. In the shown aspect of the invention,construction 10 comprises a planarized upper surface 131 at theprocessing stage of FIG. 17. Such can be formed by initially providingmaterial 130 to be over insulative material 122 as well as within theopenings 26 and 28, and subsequently planarizing the material 130 toform the planarized upper surface.

Referring next to FIG. 18, a mask 132 is formed to protect peripheralregion 4 during an etch over memory array region 6. Such etchselectively removes the material 122 relative to material 130, and thusforms openings 134, 136 and 138 extending to storage node contacts 16.In exemplary aspects of the invention, material 122 consists essentiallyof silicon dioxide and material 130 consists essentially of siliconnitride, and accordingly the selective etch utilized to form openings134, 136 and 138 is an etch selective for silicon dioxide relative tosilicon nitride.

Referring next to FIG. 19, mask 132 (FIG. 18) is removed and conductivematerial 140 is formed within the openings 134, 136 and 138. Conductivematerial 140 can comprise any suitable material, and in particularaspects will comprise, consist essentially of, or consist of metals,metal compositions and/or conductively-doped silicon. In the shownaspect of the invention, construction 10 comprises a planarized uppersurface 141. Such can be accomplished by initially forming material 140to cover materials 130 and 122, as well as extending within openings134, 136 and 138, and then subjecting construction 10 to planarizationto form the planarized upper surface extending across materials 122, 130and 140. In subsequent processing (not shown) capacitors analogous tothe capacitors of FIG. 12 can be formed on surface 141.

An advantage of the embodiment of FIGS. 13-19 relative to that of FIGS.1-12 is that it can be easier to utilize a wider variety of conductivematerials for material 140 of FIG. 19 than for the material 60 of FIG.8. Such advantage occurs because the processing of FIGS. 1-12 utilizesan etch at the processing stage of FIG. 10 which is preferably selectivefor the metal-containing bitline material 46/48/50 relative to theconductive material 60, whereas the conductive material 140 is formedafter the etch of the bitline material 100. Accordingly, the embodimentof FIGS. 12-19 eliminates dependence on the selectivity for etchingconductive material 100 relative to material 140.

FIG. 20 illustrates generally, by way of example but not by way oflimitation, an embodiment of a computer system 400 according to anaspect of the present invention. Computer system 400 includes a monitor401 or other communication output device, a keyboard 402 or othercommunication input device, and a motherboard 404. Motherboard 404 cancarry a microprocessor 406 or other data processing unit, and at leastone memory device 408. Memory device 408 can comprise various aspects ofthe invention described above. Memory device 408 can comprise an arrayof memory cells, and such array can be coupled with addressing circuitryfor accessing individual memory cells in the array. Further, the memorycell array can be coupled to a read circuit for reading data from thememory cells. The addressing and read circuitry can be utilized forconveying information between memory device 408 and processor 406. Suchis illustrated in the block diagram of the motherboard 404 shown in FIG.21. In such block diagram, the addressing circuitry is illustrated as410 and the read circuitry is illustrated as 412. Various components ofcomputer system 400, including processor 406, can comprise one or moreof the memory constructions described previously in this disclosure.

Processor device 406 can correspond to a processor module, andassociated memory utilized with the module can comprise teachings of thepresent invention.

Memory device 408 can correspond to a memory module. For example, singlein-line memory modules (SIMMs) and dual in-line memory modules (DIMMs)may be used in the implementation which utilize the teachings of thepresent invention. The memory device can be incorporated into any of avariety of designs which provide different methods of reading from andwriting to memory cells of the device. One such method is the page modeoperation. Page mode operations in a DRAM are defined by the method ofaccessing a row of a memory cell arrays and randomly accessing differentcolumns of the array. Data stored at the row and column intersection canbe read and output while that column is accessed.

An alternate type of device is the extended data output (EDO) memorywhich allows data stored at a memory array address to be available asoutput after the addressed column has been closed. This memory canincrease some communication speeds by allowing shorter access signalswithout reducing the time in which memory output data is available on amemory bus. Other alternative types of devices include SDRAM, DDR SDRAM,SLDRAM, VRAM and Direct RDRAM, as well as others such as SRAM or Flashmemories.

Memory device 408 can comprise memory formed in accordance with one ormore aspects of the present invention.

FIG. 22 illustrates a simplified block diagram of a high-levelorganization of various embodiments of an exemplary electronic system700 of the present invention. System 700 can correspond to, for example,a computer system, a process control system, or any other system thatemploys a processor and associated memory. Electronic system 700 hasfunctional elements, including a processor or arithmetic/logic unit(ALU) 702, a control unit 704, a memory device unit 706 and aninput/output (I/O) device 708. Generally, electronic system 700 willhave a native set of instructions that specify operations to beperformed on data by the processor 702 and other interactions betweenthe processor 702, the memory device unit 706 and the I/O devices 708.The control unit 704 coordinates all operations of the processor 702,the memory device 706 and the I/O devices 708 by continuously cyclingthrough a set of operations that cause instructions to be fetched fromthe memory device 706 and executed. In various embodiments, the memorydevice 706 includes, but is not limited to, random access memory (RAM)devices, read-only memory (ROM) devices, and peripheral devices such asa floppy disk drive and a compact disk CD-ROM drive. One of ordinaryskill in the art will understand, upon reading and comprehending thisdisclosure, that any of the illustrated electrical components arecapable of being fabricated to include memory constructions inaccordance with various aspects of the present invention.

FIG. 23 is a simplified block diagram of a high-level organization ofvarious embodiments of an exemplary electronic system 800. The system800 includes a memory device 802 that has an array of memory cells 804,address decoder 806, row access circuitry 808, column access circuitry810, read/write control circuitry 812 for controlling operations, andinput/output circuitry 814. The memory device 802 further includes powercircuitry 816, and sensors 820, such as current sensors for determiningwhether a memory cell is in a low-threshold conducting state or in ahigh-threshold non-conducting state. The illustrated power circuitry 816includes power supply circuitry 880, circuitry 882 for providing areference voltage, circuitry 884 for providing the first wordline withpulses, circuitry 886 for providing the second wordline with pulses, andcircuitry 888 for providing the bitline with pulses. The system 800 alsoincludes a processor 822, or memory controller for memory accessing.

The memory device 802 receives control signals from the processor 822over wiring or metallization lines. The memory device 802 is used tostore data which is accessed via I/O lines. It will be appreciated bythose skilled in the art that additional circuitry and control signalscan be provided, and that the memory device 802 has been simplified tohelp focus on the invention. At least one of the processor 822 or memorydevice 802 can include a memory construction of the type describedpreviously in this disclosure.

The various illustrated systems of this disclosure are intended toprovide a general understanding of various applications for thecircuitry and structures of the present invention, and are not intendedto serve as a complete description of all the elements and features ofan electronic system using memory cells in accordance with aspects ofthe present invention. One of the ordinary skill in the art willunderstand that the various electronic systems can be fabricated insingle-package processing units, or even on a single semiconductor chip,in order to reduce the communication time between the processor and thememory device(s).

Applications for memory cells can include electronic systems for use inmemory modules, device drivers, power modules, communication modems,processor modules, and application-specific modules, and may includemultilayer, multichip modules. Such circuitry can further be asubcomponent of a variety of electronic systems, such as a clock, atelevision, a cell phone, a personal computer, an automobile, anindustrial control system, an aircraft, and others.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1-22. (canceled)
 23. A semiconductor structure, comprising: a substratecomprising a plurality of storage node contacts within an electricallyinsulative material; a plurality of trenches within the electricallyinsulative material, the trenches having faceted top portions; aplurality of electrically conductive bitlines extending within thetrenches, the electrically conductive bitlines only partially fillingthe trenches, at least portions of individual electrically conductivebitlines being elevationally above the storage node contacts; adjacentelectrically conductive bitlines being spaced from one another byintervening locations of the electrically insulative material;insulative caps within the trenches and over the electrically conductivebitlines; and electrically conductive columns extending through theinsulative material in the intervening locations between theelectrically conductive bitlines; the electrically conductive columnsbeing electrically coupled with the storage node contacts; the facetedtop portions of the trenches sloping outwardly and upwardly frominterior regions of the trenches and having uppermost surfaces directlyagainst the electrically conductive columns.
 24. A semiconductorstructure, comprising: a substrate comprising a plurality of storagenode contacts within an electrically insulative material; a plurality oftrenches within the electrically insulative material, the trencheshaving faceted top portions; a plurality of electrically conductivebitlines extending within the trenches, the electrically conductivebitlines only partially filling the trenches, at least portions ofindividual electrically conductive bitlines being elevationally abovethe storage node contacts; adjacent electrically conductive bitlinesbeing spaced from one another by intervening locations of theelectrically insulative material; insulative caps within the trenchesand over the electrically conductive bitlines; electrically conductivecolumns extending through the insulative material in the interveninglocations between the electrically conductive bitlines; the electricallyconductive columns being electrically coupled with the storage nodecontacts; the faceted top portions of the trenches sloping outwardly andupwardly from interior regions of the trenches and having uppermostsurfaces directly against the electrically conductive columns; andwherein: an individual trench of said plurality of trenches has, in across-sectional view, a bottom periphery with a horizontally-extendingwidth; a pair of the facets are associated with said individual trenchin the cross-sectional view, with the individual facets of said pairbeing on opposing sides of the individual trench relative to oneanother; and the individual facets of the pair havehorizontally-extending widths in the cross-sectional view of from about10% to about 400% of the horizontally-extending width of the bottomperiphery.
 25. The structure of claim 24 wherein the individual facetsof the pair have horizontally-extending widths in the cross-sectionalview of from about 10% to about 50% of the horizontally-extending widthof the bottom periphery.
 26. A semiconductor structure, comprising: asubstrate comprising a plurality of storage node contacts within anelectrically insulative material; a plurality of trenches within theelectrically insulative material, the trenches having faceted topportions; a plurality of electrically conductive bitlines extendingwithin the trenches, the electrically conductive bitlines only partiallyfilling the trenches, at least portions of individual electricallyconductive bitlines being elevationally above the storage node contacts;adjacent electrically conductive bitlines being spaced from one anotherby intervening locations of the electrically insulative material;insulative caps within the trenches and over the electrically conductivebitlines; electrically conductive columns extending through theinsulative material in the intervening locations between theelectrically conductive bitlines; the electrically conductive columnsbeing electrically coupled with the storage node contacts; the facetedtop portions of the trenches sloping outwardly and upwardly frominterior regions of the trenches and having uppermost surfaces directlyagainst the electrically conductive columns; and wherein: an individualtrench of said plurality of trenches has, in a cross-sectional view, abottom periphery with a horizontally-extending width of from about 50 Åto about 5000 Å; a pair of the facets are associated with saidindividual trench in the cross-sectional view, with the individualfacets of said pair being on opposing sides of the individual trenchrelative to one another; and the individual facets of the pair havehorizontally-extending widths in the cross-sectional view of from about50 Å to about 300 Å.
 27. The structure of claim 23 wherein theelectrically conductive columns consist essentially ofconductively-doped silicon.
 28. The structure of claim 23 wherein theelectrically conductive bitlines comprise one or more of titanium,titanium nitride, tungsten nitride, tungsten silicide, and tungsten. 29.The structure of claim 23 further comprising a plurality of capacitorshaving storage nodes electrically coupled with the electricallyconductive columns, the capacitors being in one-to-one correspondencewith the electrically conductive columns.